In the semiconductor manufacturing industry, fabrication of integrated circuits on a semiconductor wafer involves a number of steps in which patterns are formed in a film of photosensitive resist, i.e. a photoresist, formed on the wafer. With the patterned formed, and void areas within the photoresist film, subsequent processing operations such as implantation of impurities, oxidation, etching and metallization may be performed. Once an integrated circuit is completely formed on a semiconductor wafer, the wafer is next assembled into a package.
In a CMOS process, transistors are typically formed by providing an active area with doped source/drain regions in the substrate, a gate insulating layer over the substrate, and a gate electrode over the gate insulating layer. Contacts (e.g., tungsten) connect the source/drain regions and gate electrode with a conductive interconnect structure having several horizontal conductive pattern layers (typically referred to as M1, M2, etc.) and vertical via layers formed within a plurality of inter-metal dielectric layers.
The standard cell configuration for an integrated circuit can be defined in a library having a rectangular pattern where the polysilicon pitch between adjacent polysilicon conductors has fixed width and/or height. A bounding box (BB) of a logic cell is the smallest rectangle that encloses all of the geometry of the cell. The cell BB is normally determined by the well layers. Cell connectors or terminals (the logical connectors) are placed on the cell abutment box (AB). The physical connector (the piece of metal to which wires are connected) normally overlaps the abutment box slightly to assure connection without leaving a tiny space between the ends of two wires. The standard cells are constructed so they can all be placed next to each other horizontally with the cell ABs touching (two cells abut).
A standard cell (a D flip-flop with clear, for example) can have some common features in a standard-cell layout. Some of those features can include connectors that are at the top and bottom of the cell on m2 on a routing grid equal to the vertical (m2) track spacing. This is a double-entry cell intended for a two-level metal process. A standard cell designed for a three-level metal process has connectors in the center of the cell. Transistor sizes can vary to optimize the area and performance but they are configured to maintain a fixed ratio to balance rise times and fall times. The cell height defined in a library are the same height with a predefined horizontal (m1) track spacing. This is close to the minimum height that can accommodate the most complex cells in a library. Power rails can be placed at the top and bottom, maintaining a certain width inside the cell and abut with the power rails in adjacent cells. The well contacts (substrate connections) are placed inside the cell at regular intervals. Additional well contacts may be placed in spacers between cells. Most commercial standard cells use m1 for the power rails, m1 for internal connections, and avoid using m2 where possible except for cell connectors.
When a library developer creates a gate-array, standard-cell, or datapath library, there is a trade-off between using wide, high-drive transistors that result in large cells with high-speed performance and using smaller transistors that result in smaller cells that consume less power. A performance-optimized library with large cells might be used for ASICs in a high-performance workstation, for example. An area-optimized library might be used in an ASIC for a battery-powered portable computer.